Circuitry for multiplication and division



Feb. 9,` 1960 E. wElss CIRCUITRY FOR MULTIPLICATION AND DIvIsIoN Filed Dec. 11, 1953 '7 Sheets-Sheet l Feb. 9, 1960 E WElss 2,924,383

CIRCUITRY FOR MULTIPLICATION AND DIVISION Filed Dec. l1, 1953 7 Sheets-Sheet 2 dfn..

L fac Feb. 9, 1960 E. wElss CIRCUITRY FOR MULTIPLIcATIoN AND DIvIsIoN Filed Dec. 11. 1953 '7 Sheets-Sheet 3 E. WEISS CIRCUITRY FOR MULTIPLICATION AND DIVISION Filed Dec. 11, .1.953

Feb. 9, 1960 '7 Sheets-Sheet 4 (aar/f wwf- Feb. 9, 1960 E. WEISS 2,924,383

CIRCUITRY FOR MULTIPLICATION AND DIVISION Filed Dec. 11. 1953 7 Sheets-Sheet 5 Feb. 9, 1960 E. wElss 2,924,383

CIRCUITRY FOR MULTIPLICATION AND DIVISION Filed Dec. 11. 1953 7 Sheets-Sheet 7 e 4235/." 424;.5 4205/.: //f/.c Zf/fgi jf/Zfffi Q7/ff? 3 Hifi s gv/g1g 49g!) C42 f5/rf United States Patent CIRCUlTRY FR MULTIPLICATION AND DIVISION Eric Weiss, Los Angeles, Calif.

Application December 11, 1953, Serial No. 397,720

i 11 Claims. (ci. 23S-159) This invention relates to digital computers and more particularly to computing circuits by which multiplying and dividing operations are carried out.

One of the objects of the invention is to provide novel multiplying-dividing circuitry in which common networks are utilized in carrying out both types of computation to the end that the structure of such circuitry is greatly simplified.

Another object of the invention is to provide a novel calculating circuit which may be selectively employed to perform multiplication or division to obtain a product or quotient, respectively.

Another object of the invention is to provide a calculating apparatus in which two numbers may be entered and in which, by the simple setting of a switch, the apparatus will generate either the product of `the two Anumbers or the quotient of one of the numbers divided by the other.

Another object. of the invention is to provide calculating apparatus whereby, in effect, both the dividing and multiplying operations are carried out by over-and-over additions.

Still another object of this invention is to provide novel circuits for performing the operations of multiplication and division on numbers represented in binary `coded decimal systems.

Generally, the present invention provides a novel arrangement of circuitry associated with a lirst, second, and third storage register to perform either the process of multiplication or division of one number by another. Simpliiication of arrangement so that common circuitry can be employed for both calculations is primarily obtained by utilizing a novel method of subtraction which is made equivalent to addition by adding the true value of the subtrahend to .the nines complement of the minuend, the sum being the nines complement of the remainder. Since the computation uses the minuend stored in its complemented form, the advantages of this approach are carried throughout the process.

As a result of the above, after having once set up the registers with the necessary digital information (i.e., complementing the dividend or the multiplier), the process of multiplication or division, as `far as the circuitry is concerned, is reduced to identical successive adding and shifting computation steps. The only dilference in the multiplication and division processes is `the criterion used to determine the 'number of times the adding step 4should be repeated before switching to the shifting step.

The state of a decision flip-flop determines this selection. Thus, when performing the process of division, the state of the decision flip-Hop during a computation step is dependent upon a previous comparison of the divisor ,digits in the second register with the true partial remainder digits obtained by complementing the digits being stored in the first register. `On the other hand, when performing the process of multiplication, the state of the decision iiip-op during a computation step is de pendent upon a previous sensing of Ithe value of the ICC digit in the controlling digital position of the'third register in which the complement of the 'multiplier is being stored.

lOther objects of the invention will be pointed out in the following description and claims and illustrated in the accompanying drawings which disclose, by way of example, the principle 'of the invention and the best mode which has been contemplated of applying that principle.

In the drawings:

Fig. l shows an overall block diagram of the circuits of the preferred embodiment of the present invention.

Fig. 2 shows a block diagram of the flip-hop circuits for the A register together with the logical equations defining their trigger inputs.

Fig. 3 is a schematic circuit diagram Vof the trigger logical networks for the A register flip-flops.

Fig. 4 shows a -block circuit diagram of the ipeop circuits for the B register together with the logical equations deiining their trigger inputs.

Fig. 5 is a schematic circuit diagram of the trigger logical networks for the B register flip-flops.

Fig. 6 shows a block diagram of the nip-flop circuits for the E register together with the logical equations defining their trigger inputs.

Fig. 7 is a schematic circuit diagram of the trigger logical networks for 4the E register flip-ops.

Fig. 8 shows a detailed circuit diagram of the E1 ip'- op circuit together with its trigger input networks.

Fig. 9 is a time chart showing waveforms explaining the operation of .the E1 flip-ilop circuit. y

Fig. l0 shows a block diagram of the K1 flip-op circuit together with the .logical equations defining'its trigger inputs. v

Fig. ll is a schematic circuit diagram of the trigger logical networks for the K1 flip-Hop. d

Fig. l2 shows a block diagram of the D1 flip-Hop circuit together with the logical equations defining its trigger inputs.

Fig. 13 is a schematic diagram of the ytrigger networks for the -Dl flip-flop.

Fig. 14 shows a table of the binary coded system used for representing the decimal digits in the present circuitry.

Fig. 15 is a diagram illustrating the mathematical procedure involved in the valuation of a problem in division.

Fig. 16 is a similar diagram illustrating the solution of a problem in multiplication.

Fig. 17 illustrates how the binary coded decimal numbers representing the dividend and the divisor are initially set-up in the A and B registers, respectively.

Referring to Fig. l, an overall schematic block diagram of the preferred embodiment of the computing circuitry of the present invention is shown. This device is comprised of an A register, a B register, and an E register which provide the means for storing numerical data lduring the computations. This numerical data is stored `therein in the binary coded decimal system.

Of these, the A and B registers function as recirculating registers which cooperate with a coded decimal summer circuit l5, to serially add the contents of the B register into the A register.

As shown in the diagram, the A register is comprised of a series of Hip-flop circuits designated A5 to A32, inelusive, together with a recirculating network 10; while the B register is comprised of a series of ilip-op circuits designated Bl to B32, inclusive, together with a recirculating network ll. During the computation period, the recirculating networks for both these registers function, in response to a steady rate of clock pulses C received from a pulse source 14, to step data being stored in each `flipop to the next in the series, stepping in order from the higher order flip-flop designations to' the lower'.

Output 12 from the A5 ip-op of the A register and v output 13 from the B5 flip-flop of the B register are connected to inputs Sb and Sb, respectively, of coded decimal summerbcircuit 15. The connection of the A5 hip-flop is direct, whereas the B5 flip-op is connected by way of a gate 17 and a mixer 18. The output S0 of the summer circuit 15 is routed as schematically indicated by a line 19 back into the A32 ilip-op, thus completing the recirculating path for the A register.

The 'data in the B5 ip-op, in addition to 'being routed into the Sb input of summer 15, is capable of being recirculated, as schematically indicated by line 20, back to the B32 flip-flop of the B register by either of twopaths. lOne of these paths connects the output of the B5 flipop through the series of four flip-flops, B4 through B1, l whse output is then connected to line 20 by Way of a 'gate 21 and a mixer 22. The other path connects the output of the B flip-flop to line 20 by way of a gate 23 and the mixer 22, thereby by-passing the series of four ip-ops B4 through'Bl.

The summer circuit 15 cyclically operates on groups Vof four serially disposed binary digits representing coded decimal digits received on its inputs Sa and Sb to generate groups of four serially disposed binary digits on output S0 corresponding to their sum. The summer circuit 15 -has a four clock pulse period delay. Thus, when it is desired to add corresponding digits of the B register into the A register, and simultaneously recirculates the con 'tents of the B register such that its digits are not shifted with respect to the sum digits, gates 17 and 21 are opened.

'This permits the binary digits on the output o'f the B5 ip-op to be fed into the summer circuit 15 and simultaneously recirculated in the B register by Way of the series of flip-ops B4 down through B1. Stepping the `data through these latter Hip-flops provides the four clock pulse delay needed in the B register recirculation to match the four clo'ck pulse delay imposed on the sum digits being introduced into the A register recirculation path by the summer circuit 15.

" lWhen it isdesired to inhibit the addition process from :taking place, that is, recirculate the contents of the A register without change, and simultaneously recirculate the lcontents of the B register such that its binary digits are shifted four binary positions, or one decimal digit, ahead o'f corresponding digits being recirculated in the A register, gates 25 and 23 are opened. Gate 25 permits a series of binary digits represented by the voltage on a line F2 `to pass into the summer 15. This output F2 corresponds to the output of the F2 ip-flop of an F counter which operates in such a manner during the computation periods as td generate successive groups of binary digits "equivalent to coded decimal digits zero (Fig. 14). The introduction of the decimal digits zero on input Sb thus results in passing the digits of the A register through the the coded decimal summer 15 without change. As previously described, gate 23 permits digits set-up in the B5 Hip-flop to be recirculated in the B register such that they counter, is provided for performing this cycle count.

This F counter is comprised of flip-flops F1 to F5, inelusive, which are interconnected by a network 27 so as to have the capacity count of 32. The counts of the F counter are indicative of the location of data in the A and B recirculating registers; or, stated in another way, each count .indicates the step of the compustation cycle through which the circuits have advanced. Of these, counts P1 and P32 of the'cycle, as well as the count periods P1 through P4, designated Pm, are necessary to the present computation and are evidenced by signals on correspondingly designated lines derived from the network 27.

The rst two flip-flops, F1 and F2, of the F counter have an additional separate cyclical counter action of their own operating with a capacity of four counts; namely, jl, f2, i3, and jg. These counts are energized, in order (during the operation of the computing circuitry), to define the four binary digits representing the successive coded decimal digits being fed into the summer circuit 15. As above noted, the summer circuit 15 operates to serially receive binary coded decimal digits simultaneously o'n inputs 8l and Sb and, after a four clock period delay, to serially emit a binary coded decimal digit corresponding to the sum of the inputs. The details of the coded decimal summer 15 are not a part of the present invention and the summer may take several forms, one embodiment of which is shown, described, and claimed in Patent No. 2,775,402, issued on December 25, 1956, to' vEric Weiss.k

It is believed thatthe detailed interconnecting arrangement, using logical design techniques, of the F counter and the Q counter, is well understood in the art. Reference to details of similarly arranged counters, having various radices, can be found, for example, in Patent No` 2,644,887, issued on July 7, 1953, to Albert E. Wolfe, Jr. Furthermore, the Q counter o'f the present invention is identical to the F counter shown in the previously referenced Weiss Patent No. 2,775,402.

The output from mixer 22, in addition to being recirculated via line 20 into the B32 flip-flop of the B register, is fed by way of connection 24 into a comparing network 26 along with the output S0' from an inverter 28 which inverts the signals being fed on output S0 from the summer circuit 15.

Comparing network 26 thus operates during the divi` sion routine to compare the magnitude of the true value of ther dividend or partial remainder (as distinguished yfrom the complemented contents of the dividend or partial remainder being stored in the A register) with the true contents of the B register. Whenever the former is equal to, or greater than, the latter, a K1 flip-hop is triggered true. As will be explained in the ensuing description, during division, switch 35 connects the output of the K1 ip-op to the input of the D1 lijp-ilop such Vthat `at the end of each computing cycle, the D1 iiip-op is set in accordance with the results of the comparison during the computing cycle.

It should be noted at this point that the output 20 of the D1 Hip-flop is connected to each of the gates 17, 25, 21, and 23. The symbols for gates 17 and 21 represent gates which are open when the D1 ilip-llop is in a true state, while the symbols for gates 25 and 23 represent gates which are open when the D1 ilip-op is in a false state. It is thus obvious that the operations of these gates during each computation cycle, as above described, is controlled by the state of the D1 flip-flop.

Next to be described is the E register which is comprised of a series of flip-Hops E1 to E12, inclusive. Associated with the E register is a stepping network 29 which is actuated by clock pulses C during the rst four clock pulses of a cycle; that is, when the signal PU., is passed through a gate 32. As noted by the symbol used for gate 32, this action is dependent on the D1 flip-op being in a false state and results in stepping the contents of the E register one decimal digit position to the left, thus shifting the contents of the E1k to E4 flip-flops into the E5 to E8` flip-flops, respectively, and the contents of the E9 to E12 ip-ops, Vas schematically indicated by connection 30, into the E1 to E4 llip-ops, respectively.

As an alternate operation, the E1 to E4 flip-ops are provided with a counting network 31 which is rendered operable when the P1 pulse counts of the F counter are permitted to pass through a gate 33 into counter network 31.` This action is dependent on the D1 ip-op being in a true state and results in increasing the contents of the B1 to E4 flip-Hops by unity. It should thus be noted that the state of the D1 flip-Hop likewise controls whether the stepping network 29 or the counting network 31 is etective during a computation cycle.

In summary, the state of the D1 flip-flop during a computation cycle controls whether gates 17, 21, and 33 are opened, or whether gates 23, 25, and 32 are opened. As will be made more evident in the ensuing description, one or the other of these groups of gates is made elective in accordance with the state of the D1 flip-flop during both the multiplication and division routines.

As already stated, during division the mechanical switch 35 is set such that the D1 llip-ilop is conditioned by the results of the comparing network 26. On the other hand, during multiplication the mechanical switch 35 is set to connect the output 34 of a network 36, associated with the E3 and E4 llip-ops, to the input of the D1 dip-flop. The arrangement of network 36 is based on the fact that any time both the E3 and E4 flip-flops store a digit l therein, the coded decimal digit 9 is being stored in the E1 to E4 flip-flops (see Fig. 14). Thus, whether this content is 9 or not 9 is the criterion which determines the true or false setting, respectively, of the D1 flip-Hop during each computation cycle of the multiplication routine.

One other counter, designated the Q counter, is required as an auxiliary to performing computations on the 'present device.

the P1 pulse count of a computation cycle, dependent on the D1 flip-flop being in a false state. The Q counter operates as a means for indicating when the E register has shifted its contents left three times, and thus completed the computation. This is done by using the R3 output t-o trigger a G2 ip-op into'an ot or false state. The output 38 from the G2 flip-flop then closes clock gate 43 thus preventing clock pulses C from further 'energizing the circuitry.

As will be made clearer in the ensuing description, the A, B, and E registers, the summer circuit 15, the F counter, and thev Q counter, together with their associated networks, represent circuitry which is utilized during both the division and multiplication routine. As pointed out, the D1 flip-flop is also used during both routines to determine whether one or the other of two alternative operations is to be performed by these circuits during each of the computation cycles.

The mode of operation of the flip-flop circuits of the present invention, which represent logical propositions in the system of logic to be performed, will be made clear by first presenting a detailed description of the El flipflop circuit shown in Fig. 8.

The flip-op circuit as used in the present embodiment of the invention is well known in that it is comprised of two triodes, V1 and V2, each of which has its plate crosscoupled to the grid of the other by a resistor R in parallel with a capacitor C. The plate of each yof the triodes is connected through a separate load resistor, like resistor R1, to a positive 225 v. D.C. source, and the cathode of each triode is grounded. Each of the grids of the tubes is joined through a grid resistor, like grid resistor R2, to a negative bias of 300 v. The flip-flop circuit is further provided with triggering circuits each connected to a respective one of its grids and output circuits each connected to a respective one of its plates.

Whenever the ip-flop is considered to be in a one `State, neon light L, connected in series with a limiting resistor R0 across the left load resistor R1, lights up; and when the ip-flop is in a zero state, neon light L is out.

The output lines E1 and E1' from the E1 llip-ilop are Staken from the right and .left plates, respectively. In

Yorder to maintain the swing of the plate voltage between voltage levels +125 v. and +100 v., clamping diodes, such as diodes 39 and 40 associated with the right output El, are provided on each of the output lines.

The trigger inputs to the Hip-flop circuit are controlled by logical networks associated with the grids of the V1 and V2 tubes. The outputs of the logical networks are coupled to the respective triode ygrids through diierentiating circuit means and blocking diode means, as shown at 41 and 42, respectively, for the left grid, the grid of tube V1. As will be more clearly explained, any time all the inputs to a logical network, such as network 44, are high in potential, a pulse similar to the clock pulse C is impressed onto the differentiating network 41. 'Ihe sharp negative pulse, created by diterentiating the trailing edge of the pulse, passes through blocking diode 42 and results in triggering the E1 ip-op into a zero state` characterized by output El' being at the high potential of +125 v. and the output E1 being at the low potential of v.

In order to simplify the presentation of the invention, the remaining llip-iiop circuits of the system, which are all similar to the E1 nip-flop, are shown in block diagram form. Thus, as noted in Fig. 2, for example, each of the flip-flop block diagrams is provided with a pair of output lines. The output line having a high potential determines the eiective term of the proposition represented by the flipdlop circuit. The other output line, having necessarily a low potential, then represents the ineffective term. Furthermore, each of the ip-flop block diagrams is provided with a pair of trigger inputs, one of which controls each of the states of the ip-op circuit.

Before going further into a description of the details ot the remaining circuits of the invention, it will be pointed out how the arrangement of the inputs and the outputs of the flip-flop circuits of the present invention enables the detailed logical circuitry `for performing the present process to be defined by logical equations.

First to be noted is that the inputs and outputs of all the ip-ilop circuits of the present invention are defined in a systemmatic manner by using the following standard nomenclature: Each of the proposition ip-ilops is designated by the combination of a capital letter and a number, and the outputs of each of the flip-flop circuits are characterized by a corresponding capital letter with the number as a subscript. In order to characterize the true state output of a ilip-llop from the false, the latter is distinguished from the former by an aixed prime. Furthermore, the inputs of a flip-flop circuit which trigger it into a true or vfalse state are designated by a corresponding lower case letter with the number as a subscript. The input for rendering the ip-op false is further characterized by a subscript zero prexing the lower case letter.

A logical equation, as herein used, defines the validity of a nip-flop trigger input in terms of the validity of the proposition llip-ops. The true and false conditions of a proposition flip-flop are preferably referred to as respective terms which are represented within the circuits by DC. voltage at a specified point in the circuits. As previously stated, this voltage can exist at either of two D.C. levels, e.g., 100 v. or 125 v. When a term is effective, its voltage is at the high level of v.; and when the term is ineffective, its voltage is at the low level of 100 v.

Presented below the block diagram of the respective flip-tlop circuits are the logical equations which define the conditions as to when and how the p-flop circuits are subject to change at the end of a clock period, in accordance with the effective terms of the system, so as to perform the function desired..

A logical equation for the grid triggering of a flipop circuit consists of stating the terms which have to be effective, i.e., of a high potential during a clock period,

scribed above for the A register flip-flops.

7 in order that the iiip-opcircuit will trigger into. a particular state at the end of the clock period. Two operat-ors are used in forming the equations. The rst, logical multiplication, means that all the terms in the particular product have to be of a high potential in order to make that product effective in a particular equation. The second, logical addition, means that at least one term of the sum has to be of a high potential in order 'to make that sum elective in a particular equation.

Thus, for example, the equation:

is interpreted as meaning that the K1 flip-flop will be triggered into the true state at the end of the clock period C du-ring which the terms S and (B1D1+D5'D1) are at a high potential, where (B1D1+B5D1) itself will be of a high potential whenever both the terms B1 and D1, or both the terms B and D1 are simultaneously of a high potential (see Fig.

Reference will next be made to Fig. 2 which shows .block diagrams of the A register ilip-ilops A5, A30

to A32, inclusive, together with the logical equations which define their trigger inputs such that information ymay `be shifted toward the right, on successive clock pulses C, from each ip-flop to the next following flipop. Thus note, for example, that the true input of the -A3-1 flip-flop is defined by logical equation a31'=A32C.

This equation is no more than a statement that, whenever the A32 output is high in potential during a clock period, the A31 flip-flip will be triggered into a true state at the end of the clock pulse period or clock pulse C. Similarly, the false input of the A31 nip-ilop is defined by logical equation 0a31=A32C. This latter equation states that, whenever the A32 output is high in potential during a clock period, the A31 ip-cliop will be triggered into a false state at the end of the clock period. The trigger inputs to the A32 flip-Hop are a32=SDC and `0a32=S0C. Thus the outputs of the summer circuit;

namely, S0 and S0', are stepped at the end of clock pulse C into the A32 ip-flop. It should now be understood how the A register ilip-ops, together with the summer circuit 15, provide a recirculatin-g path for information .stored therein.

- Fig. 3 shows the logical networks; namely, product networks or and networks, such as 46, which are used to generate the trigger equations for the A register ipilops. Product network 46 is comprised of a pair of input crystal diodes 48 and 49 joined to a common junction 50 connected through a resistor R3 to the positive potential source of 225 v. These diodes are orientated `such that whenever the input signals on both diodes are l at the high potential of +125 v., the output 51, connected to common junction 50, is at the high potential of +125 v. Any time one or both of the diode inputs ping information from each-flip-op toward the one with the next lower number designation in the manner de- As previously -noted in vconnection with Fig.` l, the output of the B5 iiip-op can be routed into either the B4 flip-flop or directly into the B32 llip-op, depending on the state of the D1 flip-flop. The rst set of trigger equations in Fig. 4 describes the recirculating action when the Dl Aflip-dop is in a true state, thus causing the output of ip-op B1 to lbe routed into the B32 iiip-op as indi- .f cated by equations: -fb32=B1-D1C and b32=B1D1'C. The

- B31 iiip-ops once.

. neously.

second set of trigger equations. describe the recirculating action when the D1 filip-flop is in a falsev state, thus causingthe output of hip-flop B5 to be routed into the B32 iiip-op. The latter action is described by trigger equa.- OIS: b32=B5D1C and 0b32=B5/D1,C. Should be understood that although two sets of equations are shown, the only variation in the trigger equations is for the B32 flip-flops. Hence the logical network for generating these equations, as shown in Fig. 5, need merely provide for generating the equations for the B5, B30 and The alternative of stepping information into the B32 flip-op from either flip-'flop Bil or B5 is handled by feeding the outputs of these ip-iiops into a logical sum netwonk, such as network 53. This sum network or or network is comprised of a pair of input crystal diodes '54 and 5S joined to a common junction 56 which is returned to ground through a resistor R4. These diodes are orientated so that whenever the signals on either one of the inputs is at the high potential of vf., the output `57 of the sum circuit, connected to the common junction 56, is at the high potential of +125 v. When neither of the inputs is high inl potential, the output 57 is at the low potential of +100 v.

Referring to Fig.i 6, the block diagrams are shown for the E register flip-flops E1 to E5 E12. These ipiiops, likewise, each have a pair of outputs and a pair of inputs designated in accordance with the standards previously described. The logical equations below the E flipiops indicate that the counting function is performed by counter 5S, which comprises only flip-ops E'l to E4; while the shifting function is performed by the use of al1 the nip-flops in the E register.

The counter arrangement of flip-flops E1 to E4 is a parallel one in that the pulses to be counted; namely, the P1 pulses, are applied to all the flip-flop inputs simulta- The interconnections of the ilip-fiop output, however, only allow certain flip-flops to be triggered by the successive P1 pulses so as to change their states in an orderly fashion to indicate the successive decimal digit outputs in accordance with the table of Fig. 14. This table shows a well-known binary coded decimal system for representing digits. A

To understand this counter arrangement, it should be noted that the connections of the outputs of the flip-flops to the right input of a particular flip-flop, i.e., the input which when energized will trigger the flip-hop in question into a true state, are determined by examining the' states of all the iiip-liops whenever the flip-flop in question is to change from a zero to a one On the other hand, the connections of the outputs of the flip-flops to the left input of a particular ip-op, i.e., the input which renders the nip-flop false, are determined by examining the states of all the ip-ilops whenever the iiip-flop in question is to change froma one to a zero The coincidence of these ilip-op states are thus represented as logical products made up of the terms representing the hip-flop outputs. For example, examine the states of the hip-flops in the table when it is desired to trigger the E1 Hip-flop into a true state, i.e., have a one therein on occurrence of the next P1 pulse. It is noted that a suficient condition is that the E1 flip-flop be in a false state and the D1 flip-flop be in a true state. Thus ii OHOWS that elzEllPlDlC. i

The trigger equations for the remaining flip-flops, E2, E3, and E4, are determined in a similar manner.

The second set of equations for the E ip-ops functions to shift the contents of the E register one decimal digit, that is, four binary positions to the left, during pulse times P1 ,4 lof the computation cycles. This action is dependent on the D1 flip-flop being in a false state. Thus it should be noted that each of the trigger equations for this action includes the outputs of the flip-flop to the right (as shown in Fig. 6) in a similar manner in which the shift trigger equations for the A and 'B registers include the `outputs of the 'flip-.Hop to the left '.(as shown in Figs.

2 and 4). The stepping action of the E register, however, is limited to the pulse periods Pm, and consequently is not a continuous recirculation action. The logical networks for generating the trigger equations for the E register llip-ops are shown in Fig. 7 and will not be-further described except for stating that, since the counting logical equations can be most conveniently generated by a cascade type of network, they are so grouped together and generated by the network at the lower right of Fig. 7. v

The block diagram of the K1 flip-flop, together with its trigger equations, is shown in Fig. l0. This ip-flop, which is used only during the division routine, is initially reset into a true state at the beginning of each computation cycle as evidenced by the reset equation k1=P32C. During each computation cycle, the binary digits on the output So'from the summer 15, as represented by their logical inverse S', are compared with the B register data taken from mixer 22. This B register data may be either the B1 ip-op output or the BS flip-flop output, depending on whether the D1 ip-op is true or false. Thus when the D1 output is high in potential (+125 v.), gate 21 (Fig. l) is open and the K1 ip-op is triggered true by equation k1=S0B1D1 and triggered false by equation Uk1=S0B1D1- The S0 output represents the waveform of the complement of the number content of the A register, corresponding to the dividend or partial remainder. This dividend was originally complemented when the circuits were initially energized. Inverting the output S0 of the summer 15 by means of inverter 28 results in uncomplementing the number being recycled back into the A register. This uncomplemented number is represented by waveform S0. On comparing the series of digits when term D1 is high in potential, depending on whether SOBl' or S0B1 is the last set of conditions to be true, as `observed through pulse time P23 of the computation cycle, the K1 ilip-op is set true or false, respectively.

Similarly, when term D1 is high in potential, depending on whether S0B5 or S0B5 is the last set of conditions to be true, as observed through pulse time P23 of the computation cycle, the K1 flip-flop is set true or false, respectively. It should be noted that the last coded decimal digit in each of the numbers being compared is necessarily equivalent to a decimal zerof This explains the reason for stating that the comparison is made only through pulse time P23 of the cycle.

The result of the above logical combination of the .trigger inputs is that the K1 ip-flop is set true if the true form of the dividend or partial remainder is equal to or greater than the true form of the divisor (B register). This is equivalent to the K1 flip-flop being set true if the addition of the contents of the B register to the A register does not result in an overow. If the true form of the dividend or partial remainder is less than the true form of the divisor, the K1 flip-flop is set false.

The above trigger equations for the K1 ip-flop are electronically generated by the logical network shown in Fig. 11, which should now be understood in view of the prior descriptions of similar networks.

The D1 ip-op shown in Fig. 12 is set true or false at the end of the P32 pulse time of a division computation cycle, in accordance with the true or false setting, respectively, of the K1 flip-hop, as denoted by trigger equations d1=K1P32C and 0d1=K1,P32C. on the other hand, the D1 flip-flop is set at the end of P32 time of a multiplication computation cycle, in accordance with the contents of the E3-E4 ip-ops of the E register. Referring to the table in Fig. 14, whenever positions i3 and i4 of the four place binary code (as stored in ilips-ops E3 and E4) are both equivalent to a binary digit 1, the contents of the E1-E4 Hip-Hop combination is equivalent to decimal nine and the D1 flip-flop is set false at P32 pulse time a's denoted by equation 0d1=E3E4P32C. On the other hand, whenever either position i3 or i3 is equivalent potential.

to a binary digit 0, the contents of E1-E4 is equivalent' I to one of the decimal digits 0 to 8, inclusive, or not nine, and the D1 yflip-flop is set true at P32 pulse time as denoted by equation d1=(E3'+E4)P32C. As shown in Fig. 13, the setting of two way mechanical switch 35 determines whether the division or multiplication trigger equation networks are `to be connected to the input of the D1 iiip-op.

Reference will next be made to Figs. 8 and 9 together in order to further describe and clarify the action of the circuits of the present computing device. As previously described, the E1 ilip-flop of the E register has two functions. One of these is to act as the rst stage of the four stage counter 58 which includes also flip-flops E2, E3, and E4. The other is to shift or step the coded decimal digits to the left in the E register. The trigger networks for enabling the E1 ip-op to perform these functions, together with the logical equations dening them, are shown in Fig. 8 as an aid to the explanation which follows.

In Fig. 9, graphs of waveforms appearing at different points of the E1 ip-ilop are shown. The regularly recurring clock pulses as generated by pulse source 14, are shown to be a square wave. As noted in Fig. 1, depressing the initiating button 62 causes an input capacitor 64 to discharge to ground creating a sharp negative potential drop on line 65. is diterentiated by capacitor 66 and resistor 67 to form a negative pulse 68 which triggers the G1 ip-op into a true state. This action results in the G2 ip-op being turned fon so that clock gate 43 is open permitting clock pulses C to be impressed on all the networks. Depressing the initiating button 62 also causes a negative pulse IE to be generated on line 63 when mechanical switch 35 is set for multiplication. As shown in Fig. 8, this pulse IE is impressed via diodes 70 and 71 directly onto the respective grids of tubes V1 and V2, thus causing whichever tube is conducting to be cut-off, and the flip-flop to consequently change state. All of the E flip-ops in the E register have this reversing pulse IE applied simultaneously to its grids. This causes the multiplier initially placed in the E register to reset to its nines complement.

As noted by the waveforms in Fig. 9, the E1 Hip-flop is assumed to be initially storing a digit zero, i.e., tube V2 is conducting, causing output E1 to be at the low potential of v. and output E1 to be at the high potential of v. As a result of the reversing of its condition by the IE pulse, output E1 is swung to a high potential and output E1 is swung to a low potential, as shown. At the end of the rst clock period, during which G1 is swung to a high potential, output G2 of the G2 ip-ilop is rendered high in potential, thus enabling clock gate 43 (see Fig. l) to activate the computing circuitry by passing clock pulses C to all the networks, as previously described.

As noted in connection with Fig, 6, the E1 ilip-op has two alternate actions which it may follow. If the D1 Hip-flop is true during a computation cycle, thevEl llip-op will function as a stage of a counter 58 along with the E2, E3, and E4 flip-flops. On the other hand, if the D1 flip-flopl is in a false state at the beginning of a computation cycle, the trigger equations of the E1 flip-Hop function to step data from the E12 ip-op into the E1 Hip-flop during pulse periods Pm. The waveforms P1 and P1/3 are shown in Fig. 9 during each of the computation cycles designated #x and #31.

During cycle #.r, the D1 flip-flop is assumed to be in a false state, as noted by waveform D1 being at a low Thus the stepping trigger equations of the E1 ip-op are effective. These equations are oe1=E12'P1/4D1'C The waveform of Ithe combination of terms P1/.3D1C is and This drop in potential '1'1" shownt to: be equivalenttothe` rst fourvclock pulses C ofcthe cycle. Note'that it is only when. the waveforms of the. terms comprising a4 product are; all high` in` potential during a clock period that the Waveform of the combination is high in potential. The E12 flip-flop (Waveform not shown) is assumed to be storing binary digits 1, 0, 1, 1y in tha't order during pulse periodsP1, P2, P3, and P4, respectively, of cycle #Je Thus, equation e1=E12P1/.1D1C has a high potential waveform during pulseperiods P1, P3, and P1; and equation oe1=E12'P1/4D1'C has a high potential waveform during pulse period P2, as shown. These latter waveforms are dierentiatcd and the negative pulses created are applied onto the grids of tthe tubes. Thus at the end of clock periods P1, P3, and P4, negative pulses are applied onto the right grid, i.e., the grid of tube V2; and at the end of clock period P2, a negative pulse is applied onto the left grid, i.e., the grid of tube V1. This results inthe E1 dip-flop storing the binary digits 1, 0, 1, 1, in order, during pulse periods P2, P3, P4, and P5, respectively, of cycle #Je When the Dfi iiip-lop is true, i.e., output D1 is high in potential` duringV a computation cycle, the E1 flip-flop count equations, e1=E1P1D1C and 0e1=E1P1D1C, are made effective. Thus when the E1 dip-flop is in a true state at P1 time, as shown for cycle #51, equation e1=E1P1D1C is made effective, as indicated by its Waveform, causing a negative pulse to be applied ontothe left grid, i.e., the grid of tube V1, thus triggering the E1 flipflop to a false state.

It is now evident that the clock pulse periodmay be considered as dividing the timing of the circuit operations into v two distinct phases. During the rst part of aclock pulse period, when the voltage from the clock source is low, the transients of the circuitry are occurring. For reliability, `these should be completed before the leading edge of the clock pulse `C arrives. During the time of the clock pulse C, the logical networks can be thought of as observing the dip-flopsand the other sources of inputs so as to know if a pulse should pass onto the grid of any of the flip-flops. The clock pulse C must be broad enough so that, taking into account its rise time, it reaches its maximum voltage level before the end of the clock period. The clock pulse `C must also have a low impedance source, so that a square edge can be created on the trailing end of the pulse passing through the grid gates. These conditions make it possible to create, by differentiation, the negative pulse, coincident with the endof the clock period, which is needed to trigger the hip-flops.

Division The circuitry will now be described with referencek to the valuation of a problem in division, which is charactei-ized by mechanical switch 35 being properly set to connect the D1 flip-iiop to the output of the comparing network 26, and connecting the initiating pulse IA to the grid inputs of all the A register flip-flops. As shown in Fig. 15, the process is broken down by showing the contents of each of the A, B, and E registers, the count in the Q counter, and the state of the D1 flip-flop at the beginning of each cycle of the computation.

As shown in Fig. 17, initially, coded decimal digits of the dividend are assumed to have been already set-up in the A17 through A28 iiip-ops of the A register. Four dip-Hops are required to set-up each coded decimal digit, such as the binary code for decimal digit one (see Fig. 14) which is set-up in the A17 to A20 ip-ops, inclusive. The coded decimal digits zero are placed in the rst three groups of flip-flops A-A8, A9-A12, A13-A16, as well as the last group of flip-flops A29A32- In addition the summer 15 is assumed to be initially storing a coded decimal digit zero therein. The coded decimal digits of the divisor are located in theB17 through B28 flipiiop-posi-tions inthe B, register, and the remaininggroups 122 of-B dip-flops, including the: firstgroup, IBI-B4, have binary coded. decimal digitsY zero set-up. therein.-

TheE register and the Q counter are initially cleared to a.y zero content, while the D1 flip-hop is set to start off in a false stateas represented by term D1' being high in potential. Additionally, the P counter is set to indicate the P1 count.

Upon thedepressing of the initiating button 62, a negative. pulse is impressed on the IA output of the initiating circuit (Fig. 1) which causes all the A register flip-flops, aswell as the contents of summer 15, to change their state. This results in the nines complement of the dividend beingy set-up in the A register as indicated in Fig. 17.' In addition, the depressing of the initiating button 62, as previously described, causes-fiip-ilops G1 and G2 to be activated, in turn, thus opening clock gate 43 which passes clock pulses `C to all the networks.

During each cycle of the division routine that the D1 flip-flop. is false, as a result of the comparison made during the previous computation cycle, the following actions take place:

(1) The divisor in the B register is inhibited from being receivedat the summer 15 and instead a binary code representing the decimal digit zero is fed into the S1, input of the summer 15. This results inthe complement of the dividend, or partial remainder, being recirculated in the A register without change.

(2) The divisor in the B register is stepped ahead one decimal digit position by routing the contents of the B5 flip-dop, rather lthan the B1 ip-fiop, back into the B32 ilip-op of the B register.

(3) The quotient in the E register is stepped one decimal digit to the left during P1/.1 pulse times.

When, as a result of the comparison at the end of a computation cycle, i.e., P32 pulse time, the D1 flip-Hop is in a true state, the following actions occur during the succeeding cycle:

(l) The contents of the B5 flip-flop (divisor) is stepped into the summer on line Sb and added` therein tov corresponding digits of. the complement of the dividend as received on line Sa. from the A5 flip-flop of the A register. This sum (representing the complement of the partial remainder) is routed back into the A32 dip-flop of the A register.

(2) The quotient digit in the E1 through E4. iiip-ops of the E register is increased by unity at P1 pulse time.

(3) The divisor digits as received from the B1 Hip-flop are rerouted back into-thesBSZ flip-hop of the B register. That is, the contents ofthe B register is recirculated withoutshift.

In addition, during each cycle that the D1 flip-flop is false, the counting network 37 of the Q counter is activatedv at P1 time, advancing rthis counter by one unit.

As aA result of these actions during each computation cycle, ythat is, the actions as determined by the D1 flip-flop being in a true state, followed by the. actions as determinedv` by the D1 flip-Hop being in a false state, each of Jthe quotient digits is built upin the iirst fouriiip-ops through E4 of the E register, and `then shifted. to the e If, for. example, a particular quotient digit should. be equivalent to a decimal 2, the D1 iiip-iiop would be true for two computation cycles, and as a result the E1-E4 flip-flops will register a binary coded decimal 2. The D1 ilip-op would then be false for the following major cycle vduring which P1/.1 pulse times thereof the contents of the Eregister is stepped to the left so as to freethe E1-E4-.ilipy-flops toV count the computation cycles indicative of the next lower order digit of the quotient.

After 3 such computation cycles, during which the D1 llip-flopis false, the-Q counter indicates its capacity count R3, which triggersoff the G2 flip-flopY simultaneously. with the. D1, flip-flop being triggered false for the fourthtime (see Fig. 13), thuspreve'nting the clock pulses C from filrthsrfatuatins the circuits,

A description of the actions whichoccur during each of the computation cycles required for the solution of the problem in division, as shown in Fig. 15, will next be presented. It should be noted that the contents or conditions of the circuits at the beginning of each of the cycles is as shown, and any changes made during a cycle are noted by observing the conditions of the circuits at the beginning of the succeeding cycle.

At the beginning of computation cycle #1, the dividend set up in the A register Hip-flop has already been inverted such that its nines complement is stored therein. The D1 ip-op is initially in a false state. Consequently the digits in the A register pass through summer 15 without change while the digits in the B register, representing the divisor, are shifted ahead one decimal digital position (as noted by observing conditions at the beginning of cycle #2) and compared in comparing network 26 with the true digits of the dividend. Note that the complement of the dividend in the A register is again complemented by inverter 28, so as to obtain the true value of the dividend for the comparison. As a result of this comparison, the dividend is found to be greater than the divisor, resulting in the K1 flip-Hop and the D1 ip-op, which follows it, ending up in a true state. In addition to the above, the Q counter advances from count R to R1 at P1 pulse time, and the contents of the E register (which at the present time is merely filled with coded decimal zeros) is shifted one decimal digital position to the left. As previously described, the E register functions to accumulate the quotient digits.

Since D1 is true coming into cycle #2, corresponding digits stored in the A and B registers are added in summer 15 and the resulting sum is rerouted back into the A register. The complement of this resulting sum is compared in comparing network 26 with the divisor digits being received from flip-Hop B1. It should be noted that the divisor digits are compared with the inverted sum digits as the latter are generated by the summer 15. Since the value of the partial remainder is greater than the divisor, the K1 flip-Hop is set true and consequently the` D1 Hip-flop remains true at P32 time. Additionally, the counting network 31 of the E register is activated :at P1 p ulse time so that the E register content becomes 001.

The D1 iiip-op being again true during cycle #3, the numbers shown are added in summer 15 as in the previous cycle. However, the comparison in this instance shows thatvthe partial remainder is less than the divisor and consequently the D1 ip-ilop ends up in a false state. The counting network 31 of the E register is again activated at P1 time resulting in its content changing to 002.

The D1 ip-op is in a false state during cycle #4 as a result of the comparison during the previous cycle. The

routine for this cycle is consequently similar to that of cycle #1, i.e., the addition is inhibited from taking place and the divisor is shifted one decimal digital position to the right. vAs a result of the comparison, the partial remainderis still found to be less than the true value of the divisor and the D1 iiip-liop remains in a false state.

During P1 time, the Q counter advances from count R1 to R2 and the contents of the E register is shifted one deci- `mal digital position to the left at P1/4 pulse times. The `content of the E register is now equivalent to 020.

During cycle #5 the D1 flip-flop is again false. Thus left such that its content is 200.

' During cycle #6, the D1 ip-op now being true, corre- ,.sponding digits in the B registers are added to the A ,register and as a result of the comparison the partial remaindei is found to be greater than the divisor resulting in the D1 ilip-op remaining true. The E register counting network 31 is activated resulting in its content being 201. The actions of cycles #7, #8, #9, and #10 are all similar to cycle #6, resulting in the E register increasing its content to 205. During the comparison of cycle #10, however, the partial remainder is found to be less than the divisor and the D1 Hip-flop ends up in a false state. This latter condition, together with the Q counter indicating an R3, operates to trigger off the G2 ip-op. This closes clock gate 43, and prevents clock pulses C from further actuating the networks, thus ending the computation. The answer to the problem is the quotient 205 as found in the E register. It should be noted that the remainder is stored in its complemented form in the A register. Y

Multiplication The operation of the circuitry will now bedescribed with reference to the solution of a problem of Ymultiplication. For this type of operation, the mechanical switch 35 is set such that the D1 iiip-op is controlled in accordance with whether the digit in the E1-E4 hip-flops of the E register is a nine or not nine. setting of the switch results in the initiating circuitry being connected such that output IE is applied to the grids of all the E register ip-ops. Initially the B register has the binary coded decimal digits of the multiplicand set up therein similarly to that described for the introduction of the divisor therein, while the multiplier digits are set up in the E register. The VA register, as well as summer 15, is cleared to indicate coded decimal zeros The A register functions to accumulate the product.

On tapping the initiating button 62, a negative pulse is impressed on output IE of the initiating circuitry (Fig. l) causing all the E register flip-Hops to reverse their state. The E register thus starts oif with the 9s complement of the true multiplier therein. This value is noted to be 896.

During each cycle of the multiplication routine that the D1 Hip-flop is false, as a result of observing the contents of the E15-E4 flip-ops during the end of the previous computation cycle, the following actions take place:

v( 1) The multiplicand in the B register is inhibited from being received at the summer 15 and instead a binary code representing the decimal digit zero is fed into the Sb input of summer 15. This results in the partial product being recirculated in the A register without change.`

(2) The multiplicand in the B register is shifted aheadl one decimal digital position by routing the contents of the B5 flip-hop, rather than the B1 Hip-flop, back into the B32 flip-Hop of the B register.

(3) The complement of the multiplier in the E register is shifted one decimal digital position to the left during P1/4 pulse times.

When, as a result of observing the contents ofthe E1-E4 Hip-flops, the D1 Hip-flop ends up in a true state, the actions during the succeeding cycle are as follows:

(1) The contents of the B5 flip-flop of the B register (multiplicand) is stepped into the summer on line Sb and added therein to corresponding digits of the partial product as received on line Sg from the A5 flip-flop of the A register.

(2) The nines complement of the multiplier digit in the E1E4 nip-flops of the E register is increased by unity at P1 pulse time.

(3) The multiplicand digits as received from the B1 flip-dop are rerouted back into the B32 Hip-Hop ofthe B register. That is, the contents of the B register is recirculated without being shifted. v

In addition, during each cycle that the D1 ipdo is false, the counting network 37 of the Q counter is activated at P1 time, advancing this counter by one unit.

The multiplication process will be further clarified by In addition, the v gea-ases description of the cycles of the routiney asset forth in Fig. 16.

At the beginning of cycle #1, the D1 Hip-flop starts out in a false state. Hence, the contents in the A register (which is equivalent to decimal zero) passes through the summer 15 without change, and the digits of the multiplicand in the B register are shifted one decimal digital position to the right. The Q counter is activated at P1 time to indicate count R1, While the shifting network of the E register shifts the decimal digits to the left during P1/.1 pulse times. ,This results in the E register content being equal to 968. The D1 flip-hop is set in accordance with the contents of theEl to E4 ip-ilops of the E register. In rthis instance, since this content is not equal to 9, the D1 nip-flop is set true at P32 tlnle. i

During cycle #2 with the D1 ilip-op true, the digits of the B register areadded into the A register which is storing the partial product. In addition a unit is added tothe E1 to E4 flip-Hops at P1 time resulting in its content changing from 8 to 9. Because the content of E1 to E4 is now equal to 9, the` D1 ip-ilop is set false at P32 Y The false state of the D1 ip-flop during cycle #3 results in an action similar to that described incyc'1e'#1. The B register is shifted one decimal digital position to the right, the Q counter advances to count R2 at P1 time, and the shifting network of the E register shifts the decimal digits therein to the left durin'gNP1/4 pulse times, causing its new content t'o lbe 699. Thus at P32 pulse time the D1 flip-flop remainsl in a. false state since the digit set up in Hip-flops E1-E4 is equivalent to decimal 9.

The false state of the D1 nip-flop during cycle #4 results in again shifting the digits in the B register, advancing the Q counter to count R3 at P1 time, and shifting the digits in the E register during Pw, time such that its contents becomes 996. Ihe D1 nip-flop is thus triggered true at P32 time since the contents of the E1 to E4 lnip-flops is less than 9.

The actions of cycles #5, #6, and #7 are all similar Asince the D1V flip-hop remains true, as indicated in Fig.

v simultaneously with the Q counter indicating an R3 count,

the G2 flip-flop is triggered into a false state at the end of the cycle. This closesclock gate 43, preventing further clock pulses C from activating the networks, and the computation stops. The answer, representing the product, is found in the A register, as indicated in Fig. 16.

It should be understood that the contents of the B register is always added into the A register to perform both the addition of its contents to the partial. product as required during multiplication, and to effectively perform the subtraction of its contents from the dividend or partial remainder as required during division. It should be noted that this method of subtraction is made equivalent `to addition by addingthe true value of the Subtrahend to the nines complement of the minuend, as long as the true value of the minuend -is greater than or equal to the subtrahend. The sum represents the'nine'is complement of the difference.

This same procedure is utilized in the E register. Thus note that a unit is always added at P1 time to the contents of the El to E4 flip-flops. Thus during division,

ythe unit is added to the true contents of the E1 to E4 the'. unit from the multiplier digits. Sincev latter op- 'eration involves eiectively subtracting afunit at a time, the test, as to when the true value of they minuend is no longer greater than or equal to the subtrahend (namely, unity), is derived by noting when the complemented form of the minuend is equal to nine, which is the same as determining when the true form of the minuend is equal to zero.

While the ycircuits as shown and described herein are admirably adapted to fulfill the objects and features of advantage previously enumerated as desirable, it is to be understood vthat the invention is not to be limited to the 'specific features shown but that the means and construction herein disclosedr are susceptible of modification in form, proportion, and arrangement of parts without departing from the principle involved or sacrificing any of its advantages, andthe invention is therefore intended to include embodiments of various forms all coming within the scope of the claims which follow.

What is claimed is:

1. An electronic calculating device comprising first, second, and third digit shifting and storage register means each arranged and "adapted for cyclicallyrecirculating signals indicative of binary coded decimal digits therein; sensing means for sensing signals indicative of a binary coded digit in the rst digital position of said third register and for providing a control signal representative ofa sensing; adding means connected; to said irst register and to-said second register and said sensing means and operable during a recirculationv cycle to add the signal indication in said second register to the signal indiciation in said first register and to add a'unt to the signall indicatio'niin the iirst digital position of said third register in response to said control signal when the results of said sensing means during the previous recirculation cycle indicates the signals stored in said first digitall position of said third register represents a digit less than a digit nine; and means connected-to and responsive to said sensing means and connected to said second and third register means and operable during a recirculation cycle to cause shifting of the signals indicativeof decimal digits' in said second and third registers one decimal digital position when the result of said sensing means during the previous recirculating cycle indicates the signals in the rst digital period of said third register represents a decimal' digit nine, whereby the number of units added to the signal indication in the first digital position of said third register prior to being shifted by said shifting means represents the number of successive recirculating cycles that the signal indication of said second register is added to the first register.

2. In a calculating device rfor performing multiplication, a rst series of flip-flops for storing binary coded signals representing digits of a product to be generated; a second series of flip-flops for storing binary coded sig'- nals representing a multiplicand; a third series vof flip-hops for storing binary coded signals representing a multiplier; means for inducing inversion of the binaryv coded signals in said third series of flip-flops to cause said third series of ip-ops to store the Complement of the multiplier; summating means connected to each of said 'first and second series 'of Hip-flops for adding they binary coded signals of said second series With the binary coded signals of said rst series of iiip-iiops and including means for returning the sum signalsk to said first series of ipops; means including counting means for adding abinary unit to the first digital position ofthe third series of flipilops in response to a control signal; means for sensing the binary coded signals in the first digital position of the third series of nip-flops and producing said control signal in response thereto; meansl capable of' inducing relative shifting of the signals inthe second third series of ipdiops with respect to the' signals in the rst series of ilip-iiops; means connected to said sensingmeans andv said shiftA inducing means for rendering said shift inducing .Ingalls operable andv inhibiting said summating'ineans aaagss from operating with the signals in said second series of flip-flops and preventing said counting means from operating when the digit being sensed by said sensing means is equal to a decimal digit nine, and for rendering said summating means and counting means operable and inhibiting said shift inducing means from operating when the digit being sensed by said sensing means is less than a decimal digit nine.

3. A calculating device comprising a iirst, second, and third storage register; means for recirculating signals representing a numerical set-up in said rst and second registers; a summer included in said rst register capable of serially adding the signals set-up in said second register into said rst register; a counter included as the first digital position of said third register; means for serially cornparing the signals set-up in said second register with the nines complement of the output of said summer to determine their relative magnitude; means for sensing signals being stored in the counter of said third register; means for shifting signals in said second and third registers; abistable state control means; switching means for setting said control means in accordance with either the output of said comparing means or said sensing means; means responsive to one state of said control means to inhibit said summer and said counter from eiectively operating and to render said shifting means operable; and means responsive to the other state of said control means to render said summer and said counter operable and to inhibit said shifting means from operating, whereby when said switching means connects said comparing means to said control means, the circuits are operable to perform the process of division, andwhen said switching means connects said sensing means to said control means, the circuits are operable to perform the process of multiplication. t

4. A calculating device comprising irst, second, and third storage registers; a summer capable of adding digital signals of said second register into said first register; means including inverter means connected to said rst register by way of said summer, for producing the nines complement of the signals in said iirst register, and including means connected to the inverter means and to the second register for comparing the digital signals of said second register with the nines complement of the digital signals in said first register to determine their relative magnitude; a counting means for adding units to the digital signals in a predetermined portion of said third register; means for sensing the value of the digital signals in said predetermined portion of said third register; means for shifting signals in said second and third registers one digital position; a two state control means; switching means for setting said control means in accordance with either the output of said comparing means or said sensing means; means for rendering said summer operable only to pass signals with delay and said counting means inoperable and said shifting means operable when said control means is in one state; and means for rendering said summer and counting means operable and said shifting means inoperable when said control means is in the other state, whereby when said switching means connects said comparing means to said control means, the device is operable to perform the process of division, and when said switching means connects said sensing means to said control means, the device is operable to perform the process of multiplication.

5. In a cyclically operable calculating device for operating with excess-three binary-coded digit-representing signals stored therein, rst, second, and third recirculating storage register means; means including inverter means, connected to said rst storage register, for inverting the signals in said rst register means to provide therein the nines-complement of the signals entered therein; means for recirculating digit-representing signals in said rst and second register means; a rst adding means capable of serially adding the digit-representing 18 signals in said second storage register means to the digitrepresenting signals of said lirst storage register means during a recirculation; a second adding means capable of adding a unit to the digit-representing signals in the rst digital position of said third storage register means during a recirculation; shifting means capable of shifting digit-representing signals set-up in said second and third recirculating storage register means during a recirculation; comparator means connected to said inverter means and to said second register means lfor comparing the digit-representing signals recirculating in said second register means with the nines-complement of the digit-representing signals from the rst register means during each recirculation of said first and second register means; first control means connected to said comparator means for rendering said shifting means operable during a recirculation when said comparator means at the end of the previous recirculation indicates the nines-complement of the digit-representing signals in said first register means is less than the digit-representing signals in said second register means; and second control means for rendering both said adding means operable during a recirculation in response to said comparator means at the end of the previous recirculation indicating the nines-complement of the digit signals in said rst register means is equal to or greater than the digit signals in said second register means.

6. In a cyclically operable calculating device, rst, second, and third storage register means; means for recirculating digit-representing signals set-up in said irst and second register means; a Arst adding means capable of operating` during a recirculation to add the digit-representing Vsignals set-up in said second register means into said first register means; a second adding means capable of operating during a recirculation cycle to add a unit to the digit-representing signal set-up in the rst digital position of said third register means; means capable of operating during a recirculation cycle to shift digit-representing signals set-up in said second and third storage register means; means for sensing during each recirculation the digit signals set-up in the rst digital position of said third register means, said sensing means generating a rst type of control signal when the digit signal sensed is equivalent to a digit nine, and a second type of control signal when the digit signal sensed represents less than a digit nine; controlling means connected to said sensing means and responsive to the iirst type of said control signals for rendering said shifting means operable during a recirculation; means responsive to the second type of said control signals for rendering both said adding means operable during a recirculation; and means connected to said controlling means for counting the number of times said shifting means is rendered operable.

7. In a calculating device for performing division operations with binary-coded decimal digits represented by binary signals coded in the binary excess-three system and stored in registers in said device, first, second, and third recirculating storage register means each comprising a respective series of bistable state elements; means for inducing binary inversion of the signals stored in said rst register means to cause to be stored therein signals representing the nines-complement of the digits represented by the signals first stored therein; stepping network means each associated with a respective one of said registers for stepping binary coded decimal digit signals from one bistable state element to the next in recirculating rings, said stepping networks for at least said rst and second register means operable continually; a serial summing means included in the recirculating ring of said rst register means for adding digit signals being stepped through said second register into said first register; a counting network associated with a group of bistable state elements in said third register means; an inverter-comparator network for inverting and producing the ninescomplement of the signals from said summing means and epesses 419 serially comparing said nines-complement signals with the digit signals being stepped out of said second'register means to determine their relative magnitude; means including a decision bistable state element set in accordance with said comparing network, said decision bistable state element being operable when in one state to route digit signals being stepped through said second register means into said summing means and to activate the counting network of said third register means, and said decision bistable state element being operable when in the other state to Acontrol the stepping networks of the second and third register means lto shift the signals being stepped therein one digital position.

8. In a calculating circuit, lirst, second, and third electronic recirculating storage register means each comprising a plurality of bistable state elements; stepping networks associated with said register means, capable of stepping signals representing numerical information from one bistable state element to the next in respective closed rings, said stepping networks for at least said first and second register means normally operating continually during a calculating operation; a serial summing means connected to said irst register and means including gating means connecting the second register to the summing means, said summing means being included in the ring forming the irst register means, capable of adding signals being stepped through said second register means with those signals in said first registermeans; a counting networkassociated with predetermined bistable state elements corresponding to a digital position of said third register means; sensing network means responsive to thesignals in said predetermined bistable state elements of said third yregister means; means including a decision bistable state element means connected to and set in accordance with said sensing network, said decision bistable state element means beingconnected'to said gating means and operable when in one state to route signals being stepped through said second register means into said summing means and connected to and operable rto activate the counting network of said third register means, and said decision bistable state element means being connectedtto be operable when in the other state to enable the respective stepping networks to shift signals in said second register means one digital position relative to the signals in said first register means, and to shift signals in said third register means one digital position.

9. In an electronic calculating device, means for performing over-and-over subtraction comprising a tirst register for storing binary coded signals representing a minuend; a second register for storing binary coded signals representing a subtrahend; means for initially inverting the binary coded signals in said iirst register to set-up therein signals representing the nines complement of the minuend; means for repeated-ly adding the binary coded signals in said second register into said iirst register to produce therein cumulative signals representing successive cumulative results corresponding to thenines complement of the remainder; and means respon-V sive to the cumulative signals at the end of each addition operation for terminating said repeat addition operation when the numerical value of the binary coded signals corresponding to the true form of the result in said first register is less than the value of the binary coded signals corresponding to the subtrahend in said second register.

l0. An electronic calculating device for selectively dividing and multiplying binary-coded decimal numbers represented by binary signals coded in the binary excessthree system, comprising: iirst register means comprising a dividend-product recirculating register for storing and operating with excess-three coded binary signals; second register means comprising a` divisor-'multiplicand `recirculating register for storing and operating with` excessthree coded binary signals; third'registerxrneans comprising a quotient-multiplier recirculating register fory storing and operating with binary signals; coded-decimal summer means connected to said rst and second register means for input thereto of signals from said register means and for producing output signals for recirculation in said iirst register means; inverter-comparator means connected to said summer means and to said second register means and effective to produce rst and second types of primary control signals in response to comparisons of signals from said second register means and inversions of signals from said summer means; period counting and demarking means; counting network means connected to said third register means and operable to inccrease the count represented by the signals in said third register means for each addition in said summer means; sensing network means connected to said third register means and operable to produce first and second types of secondary control signals in dependence upon existence of rst and second signal conditions, respectively, in said third register means; clock signal means including means supplying to the several means of the device a succession of electric clock-V signals; two-condition selector means and control means connected to said selector means, operable to select either from among said primary and secondary control signals in respective rst and second procedures and including means effective in said irst procedure in response to selection of a primary control signal to induce inversion of the binary signals in said first register means and thereby cause addition in said summer means of the signals from said second register -means with the binary complement of the signals previously in said rst register means whereby the number represented in said rst register means is divided by thenumber represented in saidv second register means, and said control means including means effective insaid second procedure in response to selection of a secondary control signal to induce inversion of the binary signals in said third register means and cause addition in said summer means of the signals from said first and second register means whereby the number represented in said second register means is multiplied by the number represented in said third register means, said selector and control means including means utilizing said period counting and demarking means to induce relative signal-shifting of the signals in said second and third register means in response, respectively, to a primary control signal of the first type, and to a secondary control signal of the rst type.

l1. Apdevice as defined in claim l0, in which a primary control signal of the irst type is produced in response to comparison of signals by said inverter-comparator means, and a secondary control signal of the iirst type is produced in response to sensing a binary excess-three coded signal by said sensing network means.

References Cited in the le of this patent UNITED STATES PATENTS 2,445,215 Flory July 13, 1948 2,624,508 Dickinson lan. 6, 1953 2,641,407 Dickinson June 9, 1953 2,686,632 Wilkinson Aug. 17, 1954 2,701,095 Stibitz Feb. l, 1955 2,703,202 Cartwright Mar. 1, 1955 2,802,625 Dickinson Aug. 13, 1957 2,817,477; Williams Dec. 24, 1957 FOREIGN VPATENTS 742,869 Great Britain Oct. 3, 1952 

